1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and particularly relates to a semiconductor integrated circuit provided with a noise reduction circuit for reducing the noise of a substrate potential.
2. Description of the Related Art
FIGS. 1A and 1B are illustrative drawings showing examples of the structure of a semiconductor integrated circuit using the twin-well/triple-well process in a P-type substrate. FIG. 1A shows a twin-well structure, and FIG. 1B shows a triple-well structure. An NMOS transistor formed on a P-type substrate 10 includes a source 11 and a drain 12 made of n+ material, a gate 13 made of polysilicon, and a back gate 15 made of a p-well generally coupled to a ground potential. In the P-type-substrate-based structure as shown in this example, a p+ region 16 (n+ region in the case of an N-type-substrate-based structure) for fixing the substrate potential is formed, and is coupled to the ground potential (the power supply potential in the case of the N-type substrate-based structure).
As described above, the p-well back-gate potential 15 and the P-type-substrate potential 16 are both coupled to the ground potential. Thus, the back-gate potential and the P-type-substrate potential are generally coupled to the common ground in the twin-well-process-based structure as shown in FIG. 1A. In such a twin-well-process-based structure, however, there is a problem that the noise generated by a through current flowing through the inductance component of the package and the transistors propagates directly to the P-type substrate. Because of this, the twin-well-process-based structure is rarely used for an analog circuit sensitive to noise, and is generally used for a digital circuit.
In the case of the triple-well-process-based structure shown in FIG. 1B, on the other hand, an n-well is additionally formed beneath the p-well 14. The purpose is to separate the p+ region constituting the back gate 15 of the transistor and the P-type substrates 10 from each other by use of the added n-well, thereby reducing the propagation of noise from the P-type substrate 10 to the transistor. To this end, the p+ region constituting the back gate 15 of the transistor and the P-type substrate 10 are coupled to separate potentials, respectively. Since the n-well 17 is an n+ region, further, an n+ region 18 is formed and coupled to the power supply potential. With this provision, it is possible to reduce the propagation of noise to the transistor, which has resulted in the widespread use of the triple well process in analog circuits.
Higher speed and higher integration are required for circuits today. With such demands, it is becoming more and more difficult to reduce the influence of noise, especially high-frequency noise, in semiconductor integrated circuits having the triple-well structure. This is because there are parasitic capacitances C1 and C2 generated by a PN junction between a p region and an n region. Such parasitic capacitance may bring about a detrimental effect when an analog circuit based on the triple-well structure and a digital circuit based on the twin-well structure are present on the same substrate. For example, noise caused by a clock signal may propagate from a digital circuit having the twin-well structure to the P-type substrate, and may further propagate from the P-type substrate to an analog circuit having the triple-well structure via the parasitic capacitance. The influence of such cross-talk noise may bring about the deterioration of accuracy in the analog circuit. Such influence is especially noticeable when there is large ringing in the power supply potential due to the inductance of the package and the power supply current of the digital circuit.
Related-art technologies for suppressing the influence of such noise include a method of suppressing the propagation of noise by forming all the circuits by use of the triple-well structure. Another method is to reduce a contact resistance by providing as many contacts as possible for the substrate and wells, thereby strengthening couplings with the power supply potential and the ground. Another method is to provide a guard ring having the function to absorb noise between circuits, thereby reducing the influence of noise. In this manner, there are many technologies available for suppressing the influence of noise in the power supply (i.e., well potential) or the substrate by use of a preventative measure that removes the cause of noise generation and/or noise propagation (e.g., Patent Document 1 an Patent Document 2). However, there are few technologies available for reducing the generated noise by use of a measure that copes with the generated noise.
FIG. 2 is a block diagram showing an example of the construction of a circuit that reduces generated noise (Patent Document 3). The noise reduction circuit shown here is formed on an integrated circuit 6 which includes a noise source circuit 4 and a circuit 5 subject to the influence of the noise, and includes a noise detecting unit 1, a noise offset signal receiving unit 2, and a noise offset signal generating circuit 3. The noise offset signal generating circuit 3 is implemented by use of an inverted amplifier circuit, and compares the substrate potential with an internal or external stable ground potential, thereby performing feedback control by use of the amplifier such as to eliminate the potential difference. In this manner, the output potential of the inverted amplifier circuit is forced to set to the ground potential. This output potential is coupled to the substrate potential to reduce substrate noise.
[Patent Document 1] Patent Application Publication No. 2000-208708
[Patent Document 2] Patent Application Publication No. 2001-28423
[Patent Document 3] Patent Application Publication No. 8-84061
The circuit shown in FIG. 2 operates based on the current noise condition detected by the noise detecting unit 1, and needs to be designed such as to provide a noise reducing effect with respect to all high-frequency noises across the entire range. Further, since the output of the inverted amplifier circuit of the noise offset signal generating circuit 3 is set to the substrate potential (ground potential), the operating range of the circuit is near the ground potential. Because of this problem of high-frequency characteristics and the problem of the operating range, there is a limit to this circuit as to its noise reduction effect.
Accordingly, there is a need for a semiconductor integrated circuit provided with a noise reduction circuit that can effectively reduce noise generated in the substrate and power supply.